Instruction Manual

We developed the Open-NVM platform in a Windows 7 environment.


The whole scheme has been evolved with the main apparatus of:

  1. FPGA Development Boards: Configured for NVM Memory Controller.
  2. Daughter Board: PCB to Connect NVM with Controller.
  3. PC/Laptop: i) For Configuring FPGA ii) Providing Host-Apps for User-interactive-mode.
    Not to mention, we will also need:
  4. Accessories (PC-peripherrals)
  5. Connectors (USB, VHDCI etc)


  1. Required Tools

    • Xilinx ISE: For using with Nexys 3 board. In our case, we've developed with WebPACK edition.
    • Digilent Adept: For downloading Verilog compiled(synthesized) binary image to Nexys 3 board.
  2. Connection of the Nexys 3 board

    • Connect both of USB connectors to PC.
      • JTAG download port
      • USB-to-Serial port
    • Note the COM port number of USB-to-Serial from 'Device Manager' of your system.
  3. Usage

    1. Launch the Project Navigator tool.
    2. Create a project for Nexys 3 board configuration.
    3. Add Verilog source files(.v) into the project.
    4. Execute Generate Program file in 'Design' window.
    5. Download Program file (.bit) to Nexys 3 board by using Digilent Adept.
      • 7-segment will show the number after downloading.
    6. Use the host controller application.

Controller Code

  1. Required Tools

    • Python 2.7.x: Python interpreter
    • pySerial: Serial port library for Python
    • tk: tk library is already included in Python 2.7, used for simple GUI
  2. Usage

    1. Edit ofserial.cfg for serial COM port number and script file name.

      global_config = {
          'COM_PORT' : 'COM5',
          'CMD_FILE' : 'POWER_ER.act'
    2. Edit script file for operation

      actions = [
              'NAME' : 'cap_0E-ALL',
              'CMDS' : [
                          uOPER(oWR=False, oRD=False, oER=True, oRST=True),
                          uNAND(pLSB=True, pCSB=True, pMSB=True),
                          uSTART() ]
              'NAME' : 'cap_0R-FF-ALL',
              'CMDS' : [
                          uOPER(oWR=False, oRD=True, oER=False, oRST=True),
                          uNAND(pLSB=True, pCSB=True, pMSB=True, ptrn_usr0=1, ptrn_usr1=1, ptrn0=0xFF, ptrn1=0xFF),
                          uSTART() ]
    3. Run - GUI version

    4. GUI Usage

      • COM PORT: COM port selection and OPEN/CLOSE the port. If port is available, it is automatically opened on launch.
      • LOG: Log window. After running the full script, [Finish] is shown here. This is different from the output log file.
      • FILES: (not yet implemented) Script file selection.
      • CMDS: (not yet implemented) Script editor.
      • CONTROL
        • START: Start the script.
        • STOP: (not working yet) Terminate the current running.
        • TEST: (just testing button for GUI development)
    5. Tips

      • There is also command line based script file which we used in initial stage of development.
      • For debugging for serial communication, we used a serial port monitoring tool Realterm which is also an open sourced project.
  3. Script file grammar

    • Every dictionary in actions array are executed and result are saved to log files.
    • 'NAME': Log file name for saving capture result
    • 'CMDS': Series of actions for setting the configuration or doing action
    Type Description Parameters
    uADDR() Address Range (Start_Address, End_Address)
    NAND: Block Address
    MRAM: Byte Address
    uOPER() Operation Filter oWR: Write
    oRD: Read
    uLOOP() Loop Count NAND: Block Address
    uLOG() Log Frequency How frequently FPGA will return result
    0=return every result
    uNAND() NAND Options pLSB/pCSB/pMSB: Filter page type for doing operations
    ptrn_usrX: True=(user data pattern), False=(column address as data pattern)
    ptrn_usr0 is applied to even page, and ptrn_usr1 is applied to odd page
    uSTART() Start Testing Start the testing with above settings

Log Parser

  1. Required Tools
    • Python 2.7.x: Python interpreter
  2. Usage

    1. Run the parser for log file(s).

      python log_file.bin
    2. We also attached a sample batch file(parse.bat) for windows. You can easily parse the files by dragging logfiles onto this batch file.

      • Edit the path in batchfile before using it.

        C:\Python27\python.exe D:\MyProject\ %*
    3. Log file

      • For details of log file, please refer to packet structure.
      • After parsing, log file is saved as .csv format.
      • Basically, we used the Microsoft Excel for further analysis of parsed data.