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FPGA Based NVM Controller

Daughter Board (PCB) Design

Sample Evaluation Results

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FPGA Based NVM Controller

The main object of this project is to design a flexible and affordable NVM controller for emerging NVM products (e.g., MRAM, Nand Flash, PCM, etc.) that can extract all the critical characteristics and determine their performance and quality. We implemented our scheme by designing one universal NVM controller by reconfiguring the same FPGA.

FPGA Development Board: Nexys 3

The Nexys 3 is a digital circuit development platform based on the Xilinx Spartan-6 LX16 FPGA. It includes a wide range of required peripherals - 10/100 Ethernet connection, 16MB of embedded RAM, USB-UART, USB host port for mice and keyboards, high-speed expansion connector, 4-digit seven-segment display, 100MHz CMOS oscillator, and 32MB PCM memory. Nexys-3 board is utilized in order to design our NVM controller for extracting performance characteristics in an optimized and efficient way. For more information on the Nexys 3 product please visit: http://www.digilentinc.com/Data/Products/NEXYS3/

A general-purpose computer with a keyboard, mouse and monitor is used to serve the purpose of both configuring the FPGA and for providing the test instruction for the memory device under test and also collecting all the DUT characteristic data to save into it. A completely customized host application has been build into it so that the programmable directed data can be collected depending on the DUT type and test category. A customized daughterboard has been designed so that it can be connected to different types of NVM products. The daughterboard connects to the FPGA via through nexys-3 development board’s high-speed expansion connector.

  1. Manual
  2. Schematic

NVM Controller Requirements:

System Requirement: (These are determined by the FPGA and the daughter board)

  1. One single Controller that may control all (at least): MRAM, TLC-Nand, PCM etc.
  2. Number of I/O control signals = 40
  3. Vcc range 1.5V-->3.3V
  4. Oscillator range 500M
  5. Variable system clock requirement: May be
  6. May provide the Maximum current consumption from board = ~300mA
  7. Separate Vdd and Vddq requirement: May be
  8. I/O speed ~500MHz
  9. I/O Current density not significant
  10. I/O static-shock protection requirement: no
  11. Flexible Debug Facility: should

Controller Design Requirement: (These are determined by the FPGA and the daughter board)

  1. Number of gates need to design this kind of controller ~5K
  2. Number of SRAM ~2K
  3. Number of Register ~2K
  4. Clock management availability: Required

NVM Controller Design

MRAM Controller Mapping

  • Memory Map
  • Instruction Set
  • Time Control Signal
  • Operation Mode
  • Source Code

TLC-Nand Controller Mapping

  • Memory Map
  • Instruction Set
  • Time Control Signal
  • Operation Mode
  • Source Code

Configuration with ISE